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VHDL Implementation of FIFO Buffer

Study Project
October, 2002

At the register level design components such as decoders, counters, comparators, arithmetic operators, and other are used to design various digital systems. A FIFO buffer is one of the register level components, which can be used to synchronize two different timing devices. Also, it can be used to boost the signal strength of an incoming signal. FIFO buffer can be found in cache controllers, peripheral communication devices, microprocessors, and many other digital devices.


FIFO - First In First Out
Six stages or 6 registers with 8-bits - shared memory

Writing Process:

  • Write at high clock edge
  • Write only if /WE or write enable is low (active low logic)
  • Do not write if buffer is full
  • If buffer is set the FIFO_FULL set the signal to be high.

    Reading Process:
  • Read at the low clock edge.
  • Read only if /OE or output enable signal is low (active low logic)
  • Do not read if buffer is empty.
  • If empty, put "11111111" or "00000000" to the DATA_OUT

Timing Constraint: 50 ns clock cycle


The VHDL implementation of the FIFO Buffer is mainly behavioral. Behavioral in a sense that it uses processes, and the behavior of the device can be understood directly from the code. Deciding whether to write or read and setting the appropriate FIFO full or empty conditions were the "core design" issues of the implementation. Refer to the report for further details.


VHDL or (Very High Speed Integrated Circuit) Hardware Description Language is an industry standard for digital gate level circuit design. By writing code to describe the behavior of the circuit or the structure the circuit can be designed. As mentioned above, we used a behavioral implementation. THE COMPLETE CODE CAN BE FOUND IN THIS FILE fifobuffercode.html.


After properly describing the circuit in VHDL, software and hardware simulations and testing are done. The following is a one scenario tested for FIFO Buffer.


  • LowOutEn=0 for all time
  • LowWrEn=0 for first 6 pulses then turns "1" for nex 7 clk pulses at the low of the 6th clk
  • When both are low first, we expect complementary write and read.
  • At the 7th pulse writing stops, and we have read everything; EmptyBuffer should go up.
  • When empty DataOut must be "256" or "11111111".
  • When LowWrEn=0 after 7 pulses, complementary read and write must take place.


  • As expected.


Depending on the logic cells required, and the suitability of the hardware available. For this case the EPM7128SLCS4-7 was selected.

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